1. Field of the Invention
The present invention relates to capacitors, and more particularly, to a capacitor and a method for fabricating the same, which increases an effective surface area through a simplified process.
2. Discussion of the Related Art
A unit cell of a semiconductor device is generally constructed with one transistor and one capacitor for storing an electrical charge as a unit of memory. As device integration increases, the area of the unit cell decreases. However, while the capacitor's layout area should be minimized, a sufficient capacitance must be maintained. These goals may be achieved by, for example, using a thinner dielectric or higher-k dielectrics. However, a dielectric layer of an ultra thin film tends to deteriorate reliability while higher-k materials usually require special processing. Therefore, a preferred approach is to increase the capacitor's effective surface area, i.e. the total area of opposing lower and upper electrodes abutting an insulating layer.
A typical capacitor uses a polysilicon-insulator-polysilicon structure, and a method of reaching such a structure is illustrated in FIG. 1.
Referring to FIG. 1, a lower polysilicon 11, a dielectric layer 12, and an upper polysilicon 13 are sequentially deposited on a semiconductor substrate 10 where various devices, interconnection lines, and a planarization layer may be formed. The lower polysilicon layer 11 serves as the lower electrode of a capacitor, and the upper electrode may be formed by patterning an upper polysilicon 13 by a typical photolithography process.
After the upper polysilicon 13 is patterned to form the upper electrode of the capacitor on the substrate 10, the dielectric layer 12 and the lower polysilicon 11 are patterned to form the dielectric member and the lower electrode of the capacitor. Similar to the pattering of the upper polysilicon 13, the patterning of the dielectric layer 12 and the lower polysilicon 11 are performed by using a typical photolithography process, i.e. a process that involves forming a photosensitive film on the substrate 10 where the upper polysilicon 13 is patterned, exposing and developing using a mask to form a pattern of the photosensitive film, etching the dielectric layer 12 and the lower polysilicon 11 exposed by the pattern of the photosensitive film, and removing a remaining pattern of the photosensitive film.
The insulating layer 14 and the planarization layer 15 are formed on the substrate 10 where the capacitor constructed with the lower electrode, the dielectric member, and the upper electrode is formed. After that, the planarization layer 15 and the insulating layer 14 are etched to form contact holes for exposing the upper polysilicon 13 and the lower polysilicon 11. Similar to the patterning of the upper polysilicon 13, the etching of the insulating layer 14 and the planarization layer 15 is performed by using a typical photolithography process, i.e. by forming a photosensitive film, exposing and developing using a mask to form a pattern of the photosensitive film, etching the planarization layer 15 and the underlying insulating layer 14 exposed by the pattern of the photosensitive film, and removing a remaining pattern of the photosensitive film.
A conductive material filling the contact hole is then formed and patterned on the substrate 10 where the contact hole is formed. Next, a ground node 16 electrically connected to the lower polysilicon 11 and a power supply node 17 electrically connected to the upper polysilicon 13 are formed. The patterning of the conductive material may likewise be performed by using a typical photolithography process.
The method for fabricating a capacitor as described above, requires at least four photolithography steps and seven deposition steps which unduly complicate the process and increase production costs. In addition, the lower electrode and the upper electrode are stacked in a planar structure, making for a large layout of the unit cell.